1. Field of the Invention
The present invention generally relates to test structures and methods for monitoring or controlling a semiconductor fabrication process. Certain embodiments relate to a test structure formed on a wafer or a reticle as a monitor for lithography and/or etch processes.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.
As the dimensions of advanced semiconductor devices continue to shrink, process control windows are shrinking commensurately. A necessary condition for smaller design rules is the control of edge placement error (EPE). EPE can be measured as two components: critical dimension error (CDE) and pattern placement error (PPE). Both are affected by other process errors, such as lithographic dose and focus excursions, that are not measured directly by CD and overlay metrology tools. These excursions constitute a form of “hidden” error that can complicate attempts to control the lithography process. As an example, focus windows are expected to shrink from about 400 nm at the 130 nm technology node to less than 100 nm at the 65 nm node, and focus error will cause more than 50% of the CD variation.
Focus and exposure impact CD control interactively. A focus excursion at the gate level, for example, can increase both the “effective dose” and the sensitivity of the CD to small changes in dose. Focus error can defeat dose-based advanced process control (APC) algorithms by corrupting both the reference level and the slope of the dose-to-CD calibration. In addition, focus errors are a known source of sidewall angle and resist height variations that can propagate into etch, and cause “feature-limited” yield loss.
Gate CD and profile control in lithography is a particularly important APC application. For example, gate CDs and profiles control the speed binning and average selling price of advanced microprocessors, and they can have a profound effect on factory revenues. In the microprocessor case, model-based gate control loops have been shown to add as much as $2,000,000 per 1000 wafer starts. As a consequence, another component of yield (bin yield) is gaining importance. Bin yield is based on parametric performance, so control of bin yield relies more on wafer metrology than on defect inspection. Thus, in the era of accelerated shrinks and early introduction of technology nodes, yield control is driving the use of in-line metrology tools.
Accordingly, monitor and control of semiconductor processes is and will continue to be of significant importance in semiconductor development and manufacturing. Furthermore, the ability of test structures or process monitoring methods to not only detect a process excursion but to be responsive to the degree of excursion will determine how well semiconductor fabrication processes can be monitored. In addition, the degree to which the test structures and results of the process monitoring can be used to correct process excursions may, in large part, determine how successfully semiconductor fabrication processes can be performed. Consequently, significant efforts have been and will continue to be made to improve the test structures that can be used to monitor semiconductor fabrication processes.
Previously used methods include line-end shortening (LES) methods such as those developed by IBM. LES of resist features is an indicator of process window for both dose and focus. Examples of such methods and target structures used in these methods are illustrated in U.S. Pat. No. 5,629,772 to Ausschnitt and U.S. Pat. No. 6,577,406 to Bruce et al., which are incorporated by reference as if fully set forth herein. Prior work described by Ausschnitt and Bruce et al. has demonstrated the use of control targets that leverage the effect of LES.
An example of one such control target is commonly referred to as a “schnitzl.” Such a target generally includes a pair of line arrays on a clear background adjacent to a pair of trough or space arrays on a resist background. The lines and spaces have the same design size and layout. The distance between the two line arrays (L) and the two space arrays (S) becomes the control metric. Typically, the line width and pitch of the individual target lines are comparable to the minimum feature on the chip. Commonly, this method has a non-monotonic response to defocus, making it useful as an excursion monitor, but unreliable as feedback for APC systems. In addition, these methods are time consuming since they require measuring additional targets that are specialized for this task alone.
A different example of previously used methods includes phase-shift-focus (PSF) methods such as those developed by IBM. In general, using phase shifting masks, errors in the phase of the mask (non-180° shifters) would cause asymmetries of the printed image as the image was defocused. These asymmetries create a translational offset in the printed image as a function of the focus offset. The phase-shift-focus reticle employs this effect for stepper diagnostics and calibration. In the simplest implementation, a bar-in-bar overlay target is written on a reticle. Both the inner and outer bars are printed at the same time, with part of the target phase shifted by 90° and the other part unshifted. If the stepper is perfectly focused, the overlay error will be exactly zero in both x and y. If there is a focus error, the phase-shifted half of the overlay target will move relative to the unshifted part, and the resulting overlay error is a direct measure of the focus error. Examples of such PSF methods and targets are illustrated in U.S. Pat. No. 5,300,786 to Brunner et al., U.S. Pat. No. 6,667,139 to Fujisawa et al., and U.S. Pat. No. 6,710,853 to LaFontaine et al., which are incorporated by reference as if fully set forth herein.
These methods have achieved some measure of success in recent years. For example, the PSF method exhibits a linear response to defocus, thereby eliminating the “deadband” or flat zone observed in standard CD versus focus plots and enabling the use of proportional control. In addition, the PSF method allows targeting of defocus values with a resolution of about 10 nm. Furthermore, the PSF monitor patterns can be measured using a high throughput, optical overlay tool, thereby minimizing the time to data, analysis, and corrective action.
There are, however, several disadvantages to these methods. For example, these methods are based upon obsolete box-in-box target technology that is not robust during mask fabrication or wafer processing. Furthermore, because of their large size, these box-in-box targets fail to replicate effects of lithographic parameters such as lithographic lens aberrations on relatively small design rules. Therefore, traditional metrology marks are not sensitive to the same aberrations as the transistors.
There have been recent disclosures, however, which attempt to deal with this issue by making box-in-box targets, which are more device representing (or device-like) and process-robust. For ease of discussion, a “device representing” target may be defined as a target that is sensitive to the same aberrations as a particular size and pitch of the transistor. Large open spaces are also subject to the adverse effects of other processes (besides lithography) such as chemical-mechanical polishing and deposition. Further, “process-robust” targets may be defined as targets that are not adversely affected by these spurious processes. As a result, the targets are typically not optimized for the process, and therefore the fine structures of the targets may suffer from process induced biases when measured by a metrology tool. In addition, targets, which are large and cumbersome compared to actual device features being printed therewith, can be used to produce correctables, which are based on measurements thereof, that may not be ideal, or even suitable, for the process.
Accordingly, it may be advantageous to develop test structures and methods for monitoring or controlling a semiconductor fabrication process such as a lithography process that yield substantially monotonic and linear responses to variations in parameters of the process such as focus errors and that replicate the effects of process parameters on relatively small design rules.